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The SCU CPU Power Status Register specifies the state of the Cortex®‑R8 processor cores with reference to power modes.
Writes to this register are enabled when the access bit for the core is set in the SCU Access Control Register. See 9.3.9 SCU Access Control Register.
Dormant mode and powered-off mode are controlled by an external power controller. SCU CPU Status Register bits indicate to the external power controller the power domains that can be powered down.
Before entering any other power mode than Normal, the core must set its status field to signal to the power controller the mode it is about to enter. The core power down routine must then execute a DSB instruction and then a WFI entry instruction. When in WFI state, the PWRCTLOx bus is enabled and signals to the power controller what it must do with power domains. See also 2.4.1 Individual core power management.
The SCU CPU Power Status Register bits can also be read by a core exiting low-power mode to determine its state before executing its reset setup.
Offset from PERIPHBASE[31:13]:
Reset value: -
The following figure shows the SCU CPU Power Status Register bit assignments.
The following table shows the SCU CPU Power Status Register bit assignments.
Table 9-5 SCU CPU Power Status Register bit assignments
|[25:24]||Core 3 status||
Power status of core 3:
|[17:16]||Core 2 status||
Power status of core 2:
|[9:8]||Core 1 status||
Power status of core 1:
|[1:0]||Core 0 status||
Power status of core 0: