B.6 Serializing instructions

Out-of-order execution is not always possible. Some instructions are serializing. Serializing instructions force the Cortex®‑R8 processor to complete all modifications to flags and general-purpose registers by previous instructions before the next instruction is executed.

The following exception entry instructions are serializing:

  • SVC.
  • SMC.
  • BKPT.
  • Instructions that take the Prefetch Abort handler.
  • Instructions that take the Undefined Instruction exception handler.

The following instructions that modify mode or program control are serializing:

  • MSR CPSR when they modify control or mode bits.
  • Data-processing to PC with the S bit set (for example, MOVS pc, r14).
  • LDM pc ^.
  • CPS.
  • SETEND.
  • RFE.

The following instructions are serializing:

  • All MCR to CP14 or CP15 except ISB and DMB.
  • MRC p14 for debug registers.
  • WFE, WFI, SEV.
  • CLREX.
  • DSB.

The following instruction, that modifies the SPSR, is serializing:

  • MSR SPSR.
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