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Depending on the programming of the debug control registers, debug events can generate debug exceptions, that is, software Monitor debug, and make the processor enter debug state, that is, hardware halting debug.
The Cortex®‑R8 processor can handle the following debug events:
There are four watchpoints. A watchpoint event is always synchronous. It has the same behavior as a synchronous Data Abort.
If a synchronous abort occurs on a watchpointed access, the synchronous abort takes priority over the watchpoint.
If the abort is asynchronous and cannot be associated with the access, the exception that is taken is unpredictable.
Cache maintenance operations do not generate watchpoint events.
The Cortex‑R8 processor implements:
See the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition for more information.