11.8.1 Programming Control Register

The TRCPRGCTLR enables the Cortex®‑R8 processor ETM.

Usage constraints
See 11.6 Controlling ETM programming.
Available in all configurations.

Register number: 1

Base offset 0x004


Type: RW

Reset: 0x00000000

The following figure shows the TRCPRGCTLR bit assignments.

Figure 11-5 TRCPRGCTLR bit assignments
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The following table shows the TRCPRGCTLR bit assignments.

Table 11-17 TRCPRGCTLR bit assignments

Bits Name Function
[31:1] - Reserved. RAZ/WI.
[0] EN

Trace program enable:

0b0The external pin ETMIFENx is LOW, and clocks are only enabled when necessary to process APB accesses, or drain any already generated trace. Writes to most registers are ignored. This is the reset value.
0b1The external pin ETMIFENx is HIGH, and clocks are enabled except for when the CPUACTIVE input is deasserted and all trace has been drained.
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