12.4 STRT instructions

Take particular care with Non-Cacheable write accesses when using the STRT instruction.

To put the correct information on the external bus, ensure one of the following:

The following table shows Cortex®‑R8 processor modes and corresponding AxPROT values.

Table 12-13 Cortex‑R8 processor mode and AxPROT values

Processor mode Type of access Value of AxPROT
User Cacheable read access User
Privileged Privileged
User Non-Cacheable read access User
Privileged Privileged
- Cacheable write access Always marked as Privileged
User Non-Cacheable write access User
Privileged Non-Cacheable write access Privileged, except when using STRT
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