|Non-Confidential||PDF version||ARM 100400_0001_03_en|
|Home > Multiprocessing > Interrupt controller > Interrupt distributor interrupt sources|
The interrupt distributor centralizes all interrupt sources before dispatching the highest priority ones to each Cortex®‑R8 processor core.
The Cortex‑R8 processor supports only the 1-N service model.
All interrupt sources are identified by a unique ID. All interrupt sources have their own configurable priority and list of targeted Cortex‑R8 processor cores. This is a list of cores that the interrupt is sent to when triggered by the interrupt distributor.
Interrupt sources are of the following types:
In the Cortex‑R8 processor, the nFIQ input is connected both to the corresponding core and to the interrupt controller. If the interrupt controller is enabled, nFIQ is mapped to PPI, and can still cause an IRQ exception.
When a core uses the interrupt controller, rather than the legacy input in the legacy mode, by enabling its own core interface, the legacy nFIQ input is also treated like other interrupt lines and uses ID28. In this case, you can mask the legacy FIQ interrupt by setting bit of the CPSR, the F bit, so that only the interrupt line of the interrupt controller is used.
In legacy IRQ mode the legacy nIRQ input, on a per-core basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the core.
When a core uses the interrupt controller, rather than the legacy input in the legacy mode, by enabling its own core interface, the legacy nIRQ input is treated like other interrupt lines and uses ID31.