9.4.2 Interrupt distributor interrupt sources

The interrupt distributor centralizes all interrupt sources before dispatching the highest priority ones to each Cortex®‑R8 processor core.

The Cortex‑R8 processor supports only the 1-N service model.

All interrupt sources are identified by a unique ID. All interrupt sources have their own configurable priority and list of targeted Cortex‑R8 processor cores. This is a list of cores that the interrupt is sent to when triggered by the interrupt distributor.

Interrupt sources are of the following types:

Software Generated Interrupts (SGI)
Each core has private interrupts, ID0-ID15, that can only be triggered by software. These interrupts are aliased so that there is no requirement for a requesting core to determine its own core ID when it deals with SGIs. The priority of an SGI depends on the value set by the receiving core in the banked SGI priority registers, not the priority set by the sending core.
Global timer, PPI[0]
The global timer uses ID27.
A legacy nFIQ input, PPI[1]

In the Cortex‑R8 processor, the nFIQ input is connected both to the corresponding core and to the interrupt controller. If the interrupt controller is enabled, nFIQ is mapped to PPI[1], and can still cause an IRQ exception.

When a core uses the interrupt controller, rather than the legacy input in the legacy mode, by enabling its own core interface, the legacy nFIQ input is also treated like other interrupt lines and uses ID28. In this case, you can mask the legacy FIQ interrupt by setting bit[6] of the CPSR, the F bit, so that only the interrupt line of the interrupt controller is used.

Private timer, PPI[2]
Each core has its own private timers that can generate interrupts, using ID29.
Watchdog timers, PPI[3]
Each core has its own watchdog timers that can generate interrupts, using ID30.
A legacy nIRQ input, PPI[4]

In legacy IRQ mode the legacy nIRQ input, on a per-core basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the core.

When a core uses the interrupt controller, rather than the legacy input in the legacy mode, by enabling its own core interface, the legacy nIRQ input is treated like other interrupt lines and uses ID31.

Shared Peripheral Interrupts (SPI)
SPIs are triggered by events generated on associated interrupt input lines. The interrupt controller can support up to 480 interrupt input lines. The interrupt input lines can be configured to be edge sensitive (rising edge) or level sensitive (HIGH level). SPIs start at ID32. The IRQS bus generates SPIs.

Note:

The Cortex‑R8 processor does not provide internal synchronization for the interrupt signals, nIRQ, nFIQ, and IRQS.
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