11.1.1 The CoreSight™ debug environment

The Cortex®‑R8 processor ETM is designed for use with CoreSight™, an extensible, system-wide debug and trace architecture from ARM®.

See the ARM® CoreSight™ SoC-400 User Guide for more information about how to use the Cortex‑R8 processor ETM in a full CoreSight system.

A software debugger provides the user interface to the Cortex‑R8 processor ETM. You can use this interface to:

  • Configure Cortex‑R8 processor ETM facilities such as filtering.
  • Configure optional trace features such as cycle accurate tracing.
  • Configure the other CoreSight components such as the Trace Port Interface Unit (TPIU).
  • Access the core debug and performance monitor units.

A CoreSight system can provide memory-mapped access from the core to its own debug and trace components.

The Cortex‑R8 processor ETM outputs its trace stream to the AMBA® 3 Advanced Trace Bus (ATB) interfaces. The CoreSight infrastructure provides the following options:

  • Export the trace information through a trace port. An external Trace Port Analyzer (TPA) captures the trace information as the figure that follows shows.
  • Write the trace information directly to an on-chip Embedded Trace Buffer (ETB) or to system memory. You can read out the trace at low speed using a JTAG or Serial Wire interface when the trace capture is complete as the figure shows.

The debugger extracts the executed image from memory and the captured trace information from the TPA or ETB and decompresses the image to provide full disassembly, with symbols, of the code that was executed. The trace information generated by the Cortex‑R8 processor ETM gives the debugger the capability to link this data back to the original high-level source code, to provide a visualization of how the code was executed on the Cortex‑R8 processor.

The figure shows how the Cortex‑R8 processor ETM fits into a CoreSight debug environment to provide full trace capabilities in a single core system. In this example, the external debug software configures the trace and debug components through the Debug Access Port (DAP). The ROM table contains a unique identification code for the SoC and the base addresses of the components connected to the debug APB. The trace stream from the Cortex‑R8 processor ETM is replicated to provide on-chip storage using the CoreSight ETB or output off-chip using the TPIU. Cross-triggering operates through the Cross Trigger Interface (CTI) and Cross Trigger Matrix (CTM) components.

Figure 11-1 ETM system diagram for a single core Cortex‑R8 processor
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


In the figure, the arrows on the thick lines show the transaction direction on buses, from master to slave port. Each bus contains individual signals that go from master to slave and other signals that go from slave to master.

For a Cortex‑R8 processor implementation with several cores, the following options are available:

  • One ETM, statically shared between each core.
  • One ETM dedicated to each core.
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.