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The Cortex®‑R8 processor ETM is designed for use with CoreSight™, an extensible, system-wide debug and trace architecture from ARM®.
See the ARM® CoreSight™ SoC-400 User Guide for more information about how to use the Cortex‑R8 processor ETM in a full CoreSight system.
A software debugger provides the user interface to the Cortex‑R8 processor ETM. You can use this interface to:
A CoreSight system can provide memory-mapped access from the core to its own debug and trace components.
The Cortex‑R8 processor ETM outputs its trace stream to the AMBA® 3 Advanced Trace Bus (ATB) interfaces. The CoreSight infrastructure provides the following options:
The debugger extracts the executed image from memory and the captured trace information from the TPA or ETB and decompresses the image to provide full disassembly, with symbols, of the code that was executed. The trace information generated by the Cortex‑R8 processor ETM gives the debugger the capability to link this data back to the original high-level source code, to provide a visualization of how the code was executed on the Cortex‑R8 processor.
The figure shows how the Cortex‑R8 processor ETM fits into a CoreSight debug environment to provide full trace capabilities in a single core system. In this example, the external debug software configures the trace and debug components through the Debug Access Port (DAP). The ROM table contains a unique identification code for the SoC and the base addresses of the components connected to the debug APB. The trace stream from the Cortex‑R8 processor ETM is replicated to provide on-chip storage using the CoreSight ETB or output off-chip using the TPIU. Cross-triggering operates through the Cross Trigger Interface (CTI) and Cross Trigger Matrix (CTM) components.
For a Cortex‑R8 processor implementation with several cores, the following options are available: