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The Cortex®‑R8 processor is delivered as fully-synthesizable RTL and is a fully-static design. Scan-chains and test wrappers for production test can be inserted into the design by the synthesis tools during implementation.
Production test of the processor cache and TCM RAMs can be done through the dedicated, pipelined MBIST interface. To improve the potential frequency compared to adding multiplexers to the RAM modules, this interface shares some of the multiplexing present in the processor design.
The TCM RAMs can be read and written directly by the program running on the Cortex‑R8 processor. You can also use the dedicated AXI3 TCM slave interface to access the TCMs.