4.3.1 Main ID Register

The MIDR provides identification information for the Cortex®‑R8 processor, including an implementer code for the device and a device ID number.

Usage constraints

The MIDR is:

  • Only accessible in privileged mode.
  • A read-only register.

Available in all configurations.

See the c0 register summary, 4.2.1 c0 registers.

The following figureshows the MIDR bit assignments.

Figure 4-1 MIDR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the MIDR bit assignments.

Table 4-18 MIDR bit assignments

Bits Name Function
[31:24] Implementer Indicates the implementer code.
[23:20] Variant Indicates the variant number of the processor. This is the major revision number m of the rmpn revision status.
[19:16] Architecture Indicates the architecture code.
[15:4] Primary part number Indicates the primary part number.
[3:0] Revision Indicates the revision number of the processor. This is the minor revision number n of the rmpn revision status.

To access the MIDR, read the CP15 register with:

MRC p15, 0, <Rd>, c0, c0, 0 ; Read Main ID Register
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.