4.3.8 Cache Size Selection Register

The CSSELR selects the current CCSIDR.

Usage constraints
The CSSELR is only accessible in privileged mode.
Configurations
Available in all configurations.
Attributes
See the c0 register summary, 4.2.1 c0 registers.

The following figure shows the CSSELR bit assignments.

Figure 4-7 CSSELR bit assignments
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The following table shows the CSSELR bit assignments.

Table 4-24 CSSELR bit assignments

Bits Name Function
[31:4] - Reserved. UNP or SBZ.
[3:1] Level

Cache level selected, RAZ/WI.

There is only one level of cache in the Cortex®‑R8 processor so the value for this field is 0b000.

[0] InD
0b1Instruction cache.
0b0Data cache.

To access the CSSELR, read the CP15 register with:

MRC p15, 2, <Rd>, c0, c0, 0 ; Read CSSELR
MCR p15, 2, <Rd>, c0, c0, 0 ; Write CSSELR
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