11.8.33 ID Register 3

The TRCIDR3 indicates certain aspects of the Cortex®‑R8 processor ETM configuration.

Usage constraints
There are no usage constraints.
Available in all configurations.

Register number: 123

Base offset 0x1EC


Type: RO

Reset: 0xXX090004

The following figure shows the TRCIDR3 bit assignments.

Figure 11-42 TRCIDR3 bit assignments
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The following table shows the TRCIDR3 bit assignments.

Table 11-54 TRCIDR3 bit assignments

Bits Name Function

Indicates whether TRCSTALLCTLR.NOOVERFLOW is implemented:

0b0NOOVERFLOW is not implemented.
[30:28] NUMPROC Number of cores available for tracing minus 1, indicating 1-8 cores. This describes the largest valid value which can be written to TRCPROCSELR.

System support for stall control of the Cortex‑R8 processor. This is driven from the ETM SYSSTALL input pin, reflecting the system implementation:

0b0System does not support stall control of the processor.
0b1System supports stall control of the processor.

This field is used with STALLCTL. Only when both SYSSTALL and STALLCTL are 0b1 does the system support stalling of the processor.


Stall control support:

0b1TRCSTALLCTLR is implemented.

This field is used with SYSSTALL.


Synchronization period support:

0b0TRCSYNCPR is read/write.

Indicates whether TRCVICTLR.TRCERR is implemented:

0b1TRCERR is implemented.
[23:20] EXLEVEL_NS

Exception levels implemented in Non-secure state. One bit for each exception level 0-3.

0b0000No Non-secure exception levels are implemented.
[19:16] EXLEVEL_S

Exception levels implemented in Secure state. One bit for each exception level 0-3.

0b1001Secure exception levels EL0 and EL3 are implemented.
[15:12] - Reserved. RAZ/WI.
[11:0] CCITMIN

Instruction trace cycle counting minimum threshold:

0x4Minimum threshold is 4.
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