9.3.5 Master Filtering Start Address Register

The Master Filtering Start Address Register provides the start address for use with master port 1 in a two-master port configuration.

Usage constraints
This register is read-only.
Configurations
Available in all two-master port configurations. When only one master port is present, these registers are not implemented. Writes have no effect and reads return a value 0x0 for all filtering registers.
Attributes

Offset from PERIPHBASE[31:13]: 0x40

Reset value: Defined by MFILTERSTART input.

The following figure shows the Master Filtering Start Address Register bit assignments.

Figure 9-6 Master Filtering Start Address Register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the Master Filtering Start Address Register bit assignments.

Table 9-7 Master Filtering Start Address Register bit assignments

Bits Name Description
[31:20] Filtering start address

Start address for use with master port 1 in a two-master port configuration when address filtering is enabled.

This value is the value of MFILTERSTART sampled on exit from reset. The value on the input gives the upper address bits with 1MB granularity.

[19:0]   Reserved. SBZ.

See 2.5.2 AXI master port 1.

Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.