11.8.20 Sequencer State Transition Control Registers 0-2

The TRCSEQEVRn define the sequencer transitions that progress to the next state or backwards to the previous state. The Cortex®‑R8 processor ETM implements a sequencer state machine with up to four states.

Usage constraints
Can only be written when the Cortex‑R8 processor ETM is disabled.
Configurations
Available in all configurations.
Attributes

Register number: 64-66

Base offset 0x100-0x108

Name: TRCSEQEVRn

Type: RW

Reset: -

The following figure shows the TRCSEQEVRn bit assignments.

Figure 11-24 TRCSEQEVRn bit assignments
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The following table shows the TRCSEQEVRn bit assignments.

Table 11-36 TRCSEQEVRn bit assignments

Bits Name Function
[31:16] - Reserved. RAZ/WI.
[15] B TYPE

Selects the resource type to move backwards to this state from the next state:

0b0Single selected resource.
0b1Boolean combined resource pair.
[14:12] - Reserved. RAZ/WI.
[11:8] B SEL

Selects the resource number, based on the value of B TYPE:

When B TYPE is 0b0, selects a single selected resource from 0-15 defined by bits[3:0].

When B TYPE is 0b1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

[7] F TYPE

Selects the resource type to move forwards from this state to the next state:

0b0Single selected resource.
0b1Boolean combined resource pair.
[6:4] - Reserved. RAZ/WI.
[3:0] F SEL

Selects the resource number, based on the value of F TYPE:

When F TYPE is 0b0, selects a single selected resource from 0-15 defined by bits[3:0].

When F TYPE is 0b1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

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