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The interrupt controller is a single functional unit that is located in a Cortex®‑R8 processor design. There is one interrupt interface per core in the design. This implementation of the interrupt controller does not support the Security Extensions.
The interrupt controller is memory-mapped. The Cortex‑R8 processor cores access it by using a private interface through the SCU.
The interrupt controller is compliant with the ARM® Generic Interrupt Controller (GIC) v1.0 architecture. The information in this TRM describes the implementation-defined features of the interrupt controller, and does not reproduce information already in the ARM® Generic Interrupt Controller Architecture Specification.