4.3.10 Auxiliary Control Register

Auxiliary Control Register (ACTLR) characteristics and bit assignments.

The ACTLR controls:

  • QoS settings.
  • ECC checking, if implemented.
  • Allocation in one way.
  • Automatic data cache coherency.
  • Speculative accesses on AXI.
  • Broadcast of cache, branch predictor, and maintenance operations.
  • Enabling the MRP, if implemented.

The following figure shows the ACTLR bit assignments.

Figure 4-9 ACTLR bit assignments
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The following table shows the ACTLR bit assignments.

Table 4-26 ACTLR bit assignments

Bits Name Function
[31:12] - Reserved. UNP/SBZP.
[11] QoS

Quality of Service bit:

0b0Disabled. This is the reset value.
0b1Enabled.

See 8.5 System configurability and QoS.

[10] ECC on ITCM

Support for ECC on ITCM, if implemented:

0b0Disabled.
0b1Enabled.

The reset value is defined by the ITCMECCEN signal. If ECC is not implemented this bit is RAZ/WI.

[9] ECC on caches and DTCM

Support for ECC on instruction and data cache and DTCM, if implemented:

0b0Disabled. This is the reset value.
0b1Enabled.

If ECC is not implemented this bit is RAZ/WI.

[8] Alloc in one way Enable allocation in one cache way only. For use with memory copy operations to reduce cache pollution. The reset value is zero.
[7] - Reserved. SBZ.
[6] SMP

Signals if the Cortex®‑R8 processor is taking part in coherency or not.

If this bit is set, then Inner Write-Back Shareable is treated as Cacheable. The reset value is zero.

[5:4] - Reserved. RAZ/WI.
[3] MRP enable

MRP enable:

0b0Disabled. This is the reset value.
0b1Enabled.
[2:1] - Reserved. SBZ.
[0] FW

Cache maintenance broadcast:

0b0Disabled. This is the reset value.
0b1Enabled.

RAZ/WI if only one core is present.

To access the ACTLR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c1, c0, 1 ; Read ACTLR
MCR p15, 0, <Rd>, c1, c0, 1 ; Write ACTLR
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