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Auxiliary Control Register (ACTLR) characteristics and bit assignments.
The ACTLR controls:
The following figure shows the ACTLR bit assignments.
The following table shows the ACTLR bit assignments.
Table 4-26 ACTLR bit assignments
Quality of Service bit:
|||ECC on ITCM||
Support for ECC on ITCM, if implemented:
The reset value is defined by the ITCMECCEN signal. If ECC is not implemented this bit is RAZ/WI.
|||ECC on caches and DTCM||
Support for ECC on instruction and data cache and DTCM, if implemented:
If ECC is not implemented this bit is RAZ/WI.
|||Alloc in one way||Enable allocation in one cache way only. For use with memory copy operations to reduce cache pollution. The reset value is zero.|
Signals if the Cortex®‑R8 processor is taking part in coherency or not.
If this bit is set, then Inner Write-Back Shareable is treated as Cacheable. The reset value is zero.
Cache maintenance broadcast:
RAZ/WI if only one core is present.
To access the ACTLR, read or write the CP15 register with:
MRC p15, 0, <Rd>, c1, c0, 1 ; Read ACTLR
MCR p15, 0, <Rd>, c1, c0, 1 ; Write ACTLR