9.3.1 SCU Control Register

The SCU Control Register enables speculative linefills to L2 with the L2C-310 Cache Controller.

The SCU Control Register also enables:

  • IC standby mode.
  • SCU standby mode.
  • SCU tag RAM ECC support.
  • Address filtering.
  • Bus ECC and parity control.
  • Access control on master ports.
  • Cache coherency features.

The following figure shows the SCU Control Register bit assignments.

Figure 9-2 SCU Control Register bit assignments
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The following table shows the SCU Control Register bit assignments.

Table 9-3 SCU Control Register bit assignments

Bits Name Description
[31:21] - Reserved. SBZ.
[20] ECC check enable on AXI TCM slave port When set, enables ECC check on the AXI TCM slave port.
[19] ECC check enable on core 3 FPP When set, enables ECC check on the AXI fast peripheral port for core 3.
[18] ECC check enable on core 2 FPP When set, enables ECC check on the AXI fast peripheral port for core 2.
[17] ECC check enable on core 1 FPP When set, enables ECC check on the AXI fast peripheral port for core 1.
[16] ECC check enable on core 0 FPP When set, enables ECC check on the AXI fast peripheral port for core 0.
[15] ECC check enable on ACP When set, enables ECC check on the Accelerator Coherency Port (ACP).
[14] ECC check enable on MP When set, enables ECC check on the AXI master peripheral port.
[13] ECC check enable on M1 When set, enables ECC check on AXI master port 1.
[12] ECC check enable on M0 When set, enables ECC check on AXI master port 0.
[11:7] - Reserved. SBZ.
[6] IC standby enable When set, this stops the interrupt controller clock when no interrupts are pending, and no core is performing a read/write request.
[5] SCU standby enable

When set, the clock in the SCU is turned off when all cores are in WFI mode or in powerdown, there is no pending request on the ACP, if implemented, and there is no remaining activity in the SCU.

When the clock in the SCU is off, ARREADYSC, AWREADYSC, and WREADYSC on the ACP are forced LOW. The clock is turned on when any core leaves WFI mode, or if there is a new request on the ACP.

[4] - Reserved. SBZ.
[3] SCU speculative linefill enable

When set, coherent linefill requests are sent speculatively to the L2C-310 Cache Controller in parallel with the tag lookup.

If the tag lookup misses, the confirmed linefill is sent to the L2C-310 Cache Controller and receives RDATA earlier because the speculative request already initiated the data request. This feature works only if there is an L2C-310 Cache Controller in the design. When filtering is enabled, only port 0 can receive speculative linefills.

[2] SCU RAMs ECC enable

Enables ECC:

0b1ECC on.
0b0ECC off. This is the default setting.

This bit is always zero if support for ECC is not implemented.

[1] Address filtering enable

This is a read-only bit that indicates address filtering:

0b1Address filtering on.
0b0Address filtering off.

This value is the value of MFILTEREN sampled when nSCURESET is deasserted.

This bit is always zero if the SCU is implemented in the single master port configuration. See 2.5.2 AXI master port 1.

[0] SCU enable

Enables SCU:

0b1SCU enabled.
0b0SCU disabled. This is the default setting.
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