ARM® Cortex®‑R8 MPCore Processor Technical Reference Manual

Revision r0p1

Table of Contents

About this book
Implementation obligations
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1 Introduction
1.1 About the Cortex®‑R8 processor
1.2 Compliance
1.2.1 ARM® architecture
1.2.2 Trace macrocell
1.2.3 Advanced Microcontroller Bus Architecture
1.2.4 Debug architecture
1.2.5 Generic Interrupt Controller architecture
1.3 Processor features
1.4 Processor interfaces
1.4.1 AXI interfaces
1.4.2 APB Debug interface
1.4.3 ETM/ATB interface
1.4.4 CTM interface
1.4.5 PMU interface
1.4.6 Test interface
1.5 Configurable options
1.6 Redundant processor core comparison
1.6.1 Split/lock
1.7 Test features
1.8 Product documentation and design flow
1.8.1 Documentation
1.8.2 Design flow
1.9 Product revisions
2 Functional Description
2.1 About the functions
2.1.1 Processor block diagram
2.1.2 Components of the Cortex®‑R8 processor
2.2 Interfaces
2.2.1 AXI3 interface
2.2.2 Debug and PMU APB interface
2.2.3 ATB interface
2.2.4 DFT interface
2.2.5 MBIST controller interface
2.3 Clocking, resets, and initialization
2.3.1 Clocking
2.3.2 Resets
2.3.3 Initialization
2.4 Power management
2.4.1 Individual core power management
2.4.2 Power domains
2.5 Processor ports
2.5.1 AXI master port 0
2.5.2 AXI master port 1
2.5.3 AXI low-latency peripheral port
2.5.4 AXI Fast Peripheral Port
2.5.5 AXI TCM slave port
2.5.6 AXI slave Accelerator Coherency Port
2.5.7 Memory Reconstruction Port
2.5.8 Private memory region
3 Programmers Model
3.1 About the programmers model
3.2 The VFP extension
3.3 Multiprocessing extensions
3.4 Memory formats
3.5 Addresses in the processor
4 System Control
4.1 About system control
4.2 Register summary
4.2.1 c0 registers
4.2.2 c1 registers
4.2.3 c5 registers
4.2.4 c6 registers
4.2.5 c7 registers
4.2.6 c9 registers
4.2.7 c13 registers
4.2.8 c15 registers
4.2.9 System identification, control, and configuration register
4.2.10 Fault handling registers
4.2.11 MPU registers
4.2.12 Cache maintenance operations
4.2.13 Interface control and configuration registers
4.2.14 Performance monitor registers
4.2.15 Miscellaneous system control registers
4.2.16 Implementation-defined registers
4.3 Register descriptions
4.3.1 Main ID Register
4.3.2 MPU Type Register
4.3.3 Multiprocessor Affinity Register
4.3.4 Revision ID Register
4.3.5 Cache Size ID Register
4.3.6 Cache Level ID Register
4.3.7 Auxiliary ID Register
4.3.8 Cache Size Selection Register
4.3.9 System Control Register
4.3.10 Auxiliary Control Register
4.3.11 Coprocessor Access Control Register
4.3.12 MPU memory region programming registers
4.3.13 DTCM Region Register
4.3.14 ITCM Region Register
4.3.15 Power Control Register
4.3.16 Cache and TCM Debug Operation Register
4.3.17 RAM Access Data Registers
4.3.18 RAM Access ECC Register
4.3.19 ECC Error Registers
4.3.20 Configuration Base Address Register
5 Floating Point Unit Programmers Model
5.1 About the FPU programmers model
5.1.1 FPU functionality
5.2 IEEE 754 standard compliance
5.2.1 Implementation of the IEEE 754 standard
5.2.2 Supported formats
5.3 Instruction throughput and latency
5.4 FPU register summary
5.4.1 Processor modes for accessing the FPU system registers
5.4.2 Accessing the FPU registers
5.5 FPU register descriptions
5.5.1 Floating-Point System ID Register
5.5.2 Floating-Point Status and Control Register
5.5.3 Floating-Point Exception Register
6 Level One Memory System
6.1 About the L1 memory system
6.1.1 Data cache policy
6.2 Fault handling
6.2.1 Fault classes
6.2.2 Fault status information
6.2.3 Usage models
6.3 About the TCMs
6.4 About the caches
6.4.1 Cache maintenance operations
6.4.2 Cache error detection and correction
6.4.3 Data cache RAM organization
6.4.4 Cache interaction with memory system
6.5 Local exclusive monitor
6.6 Memory types and L1 memory system behavior
6.7 Error detection events
7 Fault Detection
7.1 About fault detection
7.1.1 RAM and logic protection
7.1.2 Analysis of errors
7.2 RAM protection
7.2.1 Protection method
7.2.2 RAM protection summary table
7.2.3 ECC on RAMs
7.2.4 ECC codes
7.2.5 RAM configuration
7.2.6 Performance impact
7.3 Logic protection
7.4 External memory and bus protection
7.4.1 Reporting errors
7.4.2 ECC on external AXI bus
7.5 Programmers view
7.5.1 Processor registers
7.5.2 SCU registers used in ECC
7.5.3 Error detection notification signals
7.6 Lock-step
7.7 Static split/lock
8 Determinism Support
8.1 About determinism support
8.2 Memory Protection Unit
8.2.1 Regions
8.2.2 Memory types
8.2.3 Region attributes
8.2.4 MPU interaction with memory system
8.2.5 MPU faults
8.2.6 MPU software-accessible registers
8.3 Branch prediction
8.4 Low-latency interrupt mode
8.5 System configurability and QoS
8.6 Instruction and data TCM
9 Multiprocessing
9.1 About multiprocessing and the SCU
9.2 Multiprocessing programmers view
9.3 SCU registers
9.3.1 SCU Control Register
9.3.2 SCU Configuration Register
9.3.3 SCU CPU Power Status Register
9.3.4 SCU Invalidate All Register
9.3.5 Master Filtering Start Address Register
9.3.6 Master Filtering End Address Register
9.3.7 LLP Filtering Start Address Register
9.3.8 LLP Filtering End Address Register
9.3.9 SCU Access Control Register
9.3.10 SCU Error Bank First Entry Register
9.3.11 SCU Error Bank Second Entry Register
9.3.12 SCU Debug tag RAM access
9.3.13 ECC Fatal Error Register
9.3.14 FPP Filtering Start Address Registers 0-3
9.3.15 FPP Filtering End Address Registers 0-3
9.4 Interrupt controller
9.4.1 Interrupt controller clock frequency
9.4.2 Interrupt distributor interrupt sources
9.4.3 Priority formats
9.4.4 Distributor register descriptions
9.4.5 Interrupt interface register descriptions
9.5 Private timer and watchdog
9.5.1 Calculating timer intervals
9.5.2 Private timer and watchdog registers
9.6 Global timer
9.6.1 Global timer registers
9.7 Accelerator Coherency Port
9.7.1 Coherent and noncoherent mode
9.7.2 Read accesses in coherent mode
9.7.3 Write accesses in coherent mode
9.7.4 AXI protocol configurability, xIDSC, and AxUSERSC
9.7.5 AXI protocol restrictions
9.7.6 ACP bridge
10 Monitoring, Trace, and Debug
10.1 Performance Monitoring Unit
10.1.1 PMU register mappings
10.1.2 PMU management registers
10.1.3 Performance monitoring events
10.2 Memory Reconstruction Port
10.3 Embedded Trace Macrocell
10.4 Debug
10.4.1 Debug events
10.4.2 Debug registers
10.4.3 External debug interface
10.4.4 Trigger inputs and outputs
11 Embedded Trace Macrocell
11.1 About the ETM
11.1.1 The CoreSight™ debug environment
11.1.2 Features
11.1.3 Interfaces
11.1.4 Configurable options
11.1.5 Test features
11.2 Functional description
11.2.1 Processor interface
11.2.2 Instruction trace generator
11.2.3 Data trace generator
11.2.4 FIFO
11.2.5 Resources and filtering logic
11.2.6 ATB interface
11.2.7 APB interface
11.2.8 Global timestamping
11.3 Interfaces
11.3.1 Core PMU connectivity
11.4 Clocking and resets
11.4.1 Cortex®‑R8 processor ETM clock
11.4.2 Cortex®‑R8 processor ETM low-power control
11.4.3 Cortex®‑R8 processor ETM reset
11.4.4 Access permissions and power domains
11.5 Operation
11.5.1 Implementation-defined registers
11.5.2 Precise TraceEnable events
11.5.3 Parallel instruction execution
11.5.4 Context ID tracing
11.5.5 Trace and comparator features
11.5.6 Data address range filtering
11.5.7 Interaction with the PMU
11.5.8 Packet formats
11.5.9 Resource selection
11.5.10 Trace flush behavior
11.5.11 Low-power state behavior
11.5.12 Cycle counter
11.5.13 Micro-architectural exceptions
11.5.14 Synchronization
11.6 Controlling ETM programming
11.7 ETM registers
11.7.1 Cortex®‑R8 processor ETM register summary
11.7.2 Functional grouping of registers
11.8 Register descriptions
11.8.1 Programming Control Register
11.8.2 Processor Select Control Register
11.8.3 Status Register
11.8.4 Trace Configuration Register
11.8.5 Auxiliary Control Register
11.8.6 Event Control 0 Register
11.8.7 Event Control 1 Register
11.8.8 Stall Control Register
11.8.9 Global Timestamp Control Register
11.8.10 Synchronization Period Register
11.8.11 Cycle Count Control Register
11.8.12 Branch Broadcast Control Register
11.8.13 Trace ID Register
11.8.14 ViewInst Main Control Register
11.8.15 ViewInst Include/Exclude Control Register
11.8.16 ViewInst Start/Stop Control Register
11.8.17 ViewData Main Control Register
11.8.18 ViewData Include/Exclude Single Address Comparator Register
11.8.19 ViewData Include/Exclude Address Range Comparator Register
11.8.20 Sequencer State Transition Control Registers 0-2
11.8.21 Sequencer Reset Control Register
11.8.22 Sequencer State Register
11.8.23 External Input Select Register
11.8.24 Counter Reload Value Registers 0-1
11.8.25 Counter Control Register 0
11.8.26 Counter Control Register 1
11.8.27 Counter Value Registers 0-1
11.8.28 ID Register 8-13
11.8.29 Implementation Specific Register 0
11.8.30 ID Register 0
11.8.31 ID Register 1
11.8.32 ID Register 2
11.8.33 ID Register 3
11.8.34 ID Register 4
11.8.35 ID Register 5
11.8.36 Resource Selection Registers 2-16
11.8.37 Single-Shot Comparator Control Registers 0-1
11.8.38 Single-Shot Comparator Status Registers 0-1
11.8.39 OS Lock Access Register
11.8.40 OS Lock Status Register
11.8.41 Power Down Control Register
11.8.42 Power Down Status Register
11.8.43 Address Comparator Value Registers 0-7
11.8.44 Address Comparator Access Type Registers 0-7
11.8.45 Data Value Comparator Value Registers 0-1
11.8.46 Data Value Comparator Mask Registers 0-1
11.8.47 Context ID Comparator Control Register 0
11.8.48 Context ID Comparator Value Register 0
11.8.49 Integration Mode Control Register
11.8.50 Claim Tag Set Register
11.8.51 Claim Tag Clear Register
11.8.52 Device Affinity Register
11.8.53 Software Lock Access Register
11.8.54 Software Lock Status Register
11.8.55 Authentication Status Register
11.8.56 Device Architecture Register
11.8.57 Device ID Register
11.8.58 Device Type Register
11.8.59 Peripheral Identification Registers
11.8.60 Component Identification Registers
11.8.61 Integration Test Registers
12 Level Two Interface
12.1 About the L2 interface
12.1.1 Supported AXI3 transfers
12.1.2 AXI3 USER bits
12.2 Optimized accesses to the L2 memory interface
12.2.1 Early BRESP
12.2.2 SCU speculative coherent requests
12.3 Accessing RAMs using the AXI3 interface
12.4 STRT instructions
12.5 Event communication with an external agent using WFE/SEV
12.6 Accelerator Coherency Port interface
12.6.1 ACP requests
12.6.2 ACP limitations
A Signal Descriptions
A.1 About the signal descriptions
A.2 Clock and control signals
A.3 Reset signals
A.4 Interrupt controller signals
A.5 Configuration signals
A.6 Standby signals
A.6.1 Standby and Wait for event signals
A.6.2 Event signals
A.7 Power management signals
A.8 AXI3 interfaces
A.8.1 AXI master interface signals
A.8.2 AXI fast peripheral port signals
A.8.3 AXI low-latency peripheral port signals
A.8.4 AXI TCM slave port signals
A.9 Performance monitoring signals
A.10 Exception flag signals
A.11 Error detection notification signals
A.11.1 Error detection global notification signals
A.11.2 RAM ECC error bank status signals
A.11.3 Bus ECC error signals on AXI master ports
A.11.4 Bus ECC error signals on AXI fast peripheral port
A.11.5 Bus ECC error signals on AXI low-latency peripheral port
A.11.6 Bus ECC error signals on AXI ACP slave port
A.11.7 Bus ECC error signals on AXI TCM slave port
A.11.8 Lock-step and split/lock signals
A.12 Test interface
A.13 MBIST interface
A.13.1 L1 and DTCM Cortex®‑R8 processor MBIST interface width without ECC
A.13.2 L1 and DTCM Cortex®‑R8 processor MBIST interface width with ECC
A.13.3 ITCM Cortex®‑R8 processor MBIST interface width without ECC
A.13.4 ITCM Cortex®‑R8 processor MBIST interface width with ECC
A.14 External debug signals
A.14.1 Debug enable signals
A.14.2 Debug signals
A.14.3 Miscellaneous debug signals
A.14.4 Debug APB interface signals
A.15 ETM signals
A.15.1 Processor trace interface signals
A.15.2 ETM APB signals
A.15.3 ETM ATB signals for instruction trace
A.15.4 ETM ATB signals for data trace
A.15.5 ETM Miscellaneous signals
A.15.6 CTI signals
A.16 Memory reconstruction port signals
A.17 Power gating interface signals
B Cycle Timings and Interlock Behavior
B.1 About instruction cycle timing
B.2 Data-processing instructions
B.3 Load and store instructions
B.3.1 Single load and store operation cycle timings
B.3.2 Load multiple operations cycle timings
B.3.3 Store multiple operations cycle timings
B.4 Multiplication instructions
B.5 Branch instructions
B.6 Serializing instructions
C Revisions
C.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-01 14 December 2015 Confidential First release for r0p0
0001-02 09 March 2016 Confidential First release for r0p1
0001-03 03 March 2017 Non-Confidential Second release for r0p1

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