4.2.16 Implementation-defined registers

Summary of the implementation-defined registers.

Table 4-17 Implementation-defined registers

Name CRn Op1 CRm Op2 Reset Description
PCR c15 0 c0 0 0x0 4.3.15 Power Control Register
CTDOR c1 0 UNK 4.3.16 Cache and TCM Debug Operation Register
RADRLO 1 UNK 4.3.17 RAM Access Data Registers, bits[31:0]
RADRHI 2 UNK 4.3.17 RAM Access Data Registers, bits[63:32]
RAECCRa 3 UNK 4.3.18 RAM Access ECC Register
D_ECC_ENTRY_0a c2 0 UNK 4.3.19 ECC Error Registers
D_ECC_ENTRY_1a 1 UNK
D_ECC_ENTRY_2a 2 UNK
I_ECC_ENTRY_0a c3 0 UNK
I_ECC_ENTRY_1a 1 UNK
I_ECC_ENTRY_2a 2 UNK
DTCM_ECC_ENTRYb c4 0 UNK
ITCM_ECC_ENTRYb c5 0 UNK
CBAR 4 c0 0 UNK 4.3.20 Configuration Base Address Register
a Only present if ECC is present, otherwise RAZ/WI.
b Only present if ECC and TCM are present, otherwise RAZ/WI.
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