4.3.2 MPU Type Register

The MPUIR indicates the number of MPU regions, 12, 16, 20, or 24, and the type of MPU regions, unified or separate.

Usage constraints

The MPUIR is:

  • Only accessible in privileged mode.
  • A read-only register.

Available in all configurations.

See the c0 register summary, 4.2.1 c0 registers.

The following figure shows the MPUIR bit assignments.

Figure 4-2 MPUIR bit assignments
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The following table shows the MPUIR bit assignments.

Table 4-19 MPUIR bit assignments

Bits Name Function
[31:16] - Reserved. SBZ.
[15:8] Number of MPU regions

Indicates the number of regions:

0b0001100024 regions.
0b0001010020 regions.
0b0001000016 regions.
0b0000110012 regions.
[7:1] - Reserved. SBZ.
[0] MPU region type

Specifies the type of MPU regions, unified or separate, in the processor.

Always set to 0b0 because the Cortex®‑R8 processor has unified memory regions. See 3.5 Addresses in the processor.

To access the MPUIR, read the CP15 register with:

MRC p15,0,<Rt>,c0,c0,4 ; Read CP15 MPU Type Register
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