4.3.6 Cache Level ID Register

The CLIDR indicates the cache levels that are implemented in the Cortex®‑R8 processor and under the control of the System Control Coprocessor. If caches are not implemented, this register value is 0x0.

Usage constraints

The CLIDR is:

  • Only accessible in privileged mode.
  • A read-only register.

Available in all configurations.

See the c0 register summary, 4.2.1 c0 registers.

The following figure shows the CLIDR bit assignments.

Figure 4-6 CLIDR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the CLIDR bit assignments.

Table 4-23 CLIDR bit assignments

Bits Name Function
[31:30] - UNP or SBZ
[29:27] LoU
0b001Level of unification
[26:24] LoC
0b001Level of coherency
[23:21] LoUIS
0b001Level of Unification Inner Shareable
[20:18] CL 7
0b000No cache at CL 7
[17:15] CL 6
0b000No cache at CL 6
[14:12] CL 5
0b000No cache at CL 5
[11:9] CL 4
0b000No cache at CL 4
[8:6] CL 3
0b000No cache at CL 3
[5:3] CL 2
0b000No unified cache at CL 2
[2:0] CL 1
0b000Caches not implemented
0b011Separate instruction and data caches at CL 1

To access the CLIDR, read the CP15 register with:

MRC p15, 1,<Rd>, c0, c0, 1 ; Read CLIDR
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.