4.3.14 ITCM Region Register

The ITCMRR Indicates the base address and size of the instruction TCM, and enables the Instruction TCM directly from reset.

Usage constraints

The ITCMRR is:

  • Only accessible in privileged mode.
  • For use with INITRAM0.

Available in all configurations.

See the c9 register summary, 4.2.6 c9 registers.

The following figure shows the ITCMRR bit assignments.

Figure 4-16 ITCMRR bit assignments
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The following table shows the ITCMRR bit assignments.

Table 4-34 ITCMRR bit assignments

Bits Name Function
[31:12] Instruction TCM region base address

Indicates the Instruction TCM region base address.

When INITRAM0 is HIGH and VINITH0 is HIGH for core 0, the reset value is 0xFFFF0, otherwise the reset value is 0x00000.

The same applies for core 1, 2 and 3, if present.

[11:7] - Reserved. SBZ.
[6:2] Instruction TCM size

Indicates the Instruction TCM region size:


All other values are Reserved.

[1] - Reserved. SBZ.
[0] Enable bit

Enable bit:

0b0Disabled. This is the reset value.

When INITRAM0 is HIGH this enables the Instruction TCM for core 0 directly from reset.

The same applies for core 1, 2, and 3 if present.

If Instruction TCM is not implemented, this field is Read-only and its value is 0b0.


If the processor is not configured to include an Instruction TCM, this field must not be set to 1.

To access the ITCMRR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c9, c1, 1 ; Read ITCM Region Register
MCR p15, 0, <Rd>, c9, c1, 1 ; Write ITCM Region Register
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