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The ITCMRR Indicates the base address and size of the instruction TCM, and enables the Instruction TCM directly from reset.
The ITCMRR is:
Available in all configurations.
The following figure shows the ITCMRR bit assignments.
The following table shows the ITCMRR bit assignments.
Table 4-34 ITCMRR bit assignments
|[31:12]||Instruction TCM region base address||
Indicates the Instruction TCM region base address.
When INITRAM0 is HIGH
and VINITH0 is HIGH for core 0, the reset value
The same applies for core 1, 2 and 3, if present.
|[6:2]||Instruction TCM size||
Indicates the Instruction TCM region size:
All other values are Reserved.
When INITRAM0 is HIGH this enables the Instruction TCM for core 0 directly from reset.
The same applies for core 1, 2, and 3 if present.
TCM is not implemented, this field is Read-only and its value is
Note:If the processor is not configured to include an Instruction TCM, this field must not be set to 1.
To access the ITCMRR, read or write the CP15 register with:
MRC p15, 0, <Rd>, c9, c1, 1 ; Read ITCM Region Register
MCR p15, 0, <Rd>, c9, c1, 1 ; Write ITCM Region Register