11.8.52 Device Affinity Register

The TRCDEVAFF0 enables the Cortex®‑R8 processor ETM to determine which core in the Cortex‑R8 processor the component relates to.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Register number: 1002

Base offset 0xFA8

Name: TRCDEVAFF0

Type: RO

Reset: -

The following figure shows the TRCDEVAFF0 bit assignments.

Figure 11-62 TRCDEVAFF0 bit assignments
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The following table shows the TRCDEVAFF0 bit assignments.

Table 11-75 TRCDEVAFF0 bit assignments

Bits Name Function
[31] - Indicates the register uses the new multiprocessor format. This is always 0b1.
[30] U bit

Multiprocessing Extensions:

0b0Indicates the Cortex‑R8 processor is a multiprocessor configuration.
[29:12] - Reserved. SBZ.
[11:8] Cluster ID Value read in CLUSTERID configuration pins. It identifies a Cortex‑R8 processor cluster in a system that has several Cortex‑R8 processor clusters present.
[7:2] - Reserved. SBZ.
[1:0] CPU ID

Indicates the core number in the multiprocessor configuration:

0x00Core 0.
0x01Core 1.
0x10Core 2.
0x11Core 3.
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