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The L1 memory system can be configured to include instruction and data caches of varying sizes. You can configure the size of each cache independently. The cached instructions or data are fetched from external memory using the L2 memory interface. The cache controllers use the RAMs that are integrated into the Cortex®‑R8 processor macrocell during implementation.
If an access is to Cacheable memory, and the cache is enabled, a lookup is performed in the cache and, if found in the cache, that is, a cache hit, the data is fetched from or written into the cache. When the cache is not enabled and for Non-Cacheable memory, the accesses are performed using the L2 memory interface.
The cache controllers also manage the cache maintenance operations.
Each cache can also be configured with ECC error checking schemes. If an error checking scheme is implemented and enabled, then the tags associated with each line, and data read from the cache are checked whenever a lookup is performed in the cache.
For more information on the general rules about memory attributes and behavior, see the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.