A.13.2 L1 and DTCM Cortex®‑R8 processor MBIST interface width with ECC

Details of the the L1 and DTCM signals for designs with ECC.

Table A-44 L1 and DTCM Cortex®‑R8 processor MBIST interface width with ECC

Name Type Source/destination Description
MBISTREQ1[1:0] Input MBIST controller BIST mode request signal, one per core
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