9.1 About multiprocessing and the SCU

The SCU connects Cortex®‑R8 processor cores to the memory system through the AXI3 interfaces.

The SCU functions are to:

Note:

The Cortex‑R8 processor SCU does not support hardware management of instruction cache coherency.

The SCU has an optional Accelerator Coherency Port (ACP) that is used to connect a noncached master such as a DMA to the Cortex‑R8 processor, as shown in the following figure.

Figure 9-1 SCU and ACP in a two-core configuration
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The SCU has two slave ports per core, one port connected to the instruction bus and one port connected to the data bus of each core.

The ACP is intended to be used for coherent data transfers. However, the ACP can also be used in a noncoherent mode, where any transfer with the level 2 memory can be done directly, without having to deal with data coherency.

The data coherency efficiency, either using the ACP or between individual cores, is enhanced by using the replicated tag RAMs of each L1 data cache tag RAM of each core in the SCU. Any transfer through the SCU is looked up in the replicated tag RAM to determine whether data is present in the L1 data cache of either core without having to access that cache.

You can choose to have one or two AXI master ports. The SCU also provides memory-mapped address filtering to enable you to route specific transfers on AXI master port 1 with QoS guarantees.

If address filtering is not enabled, transfers for odd-numbered cores, and instructions such as SWP, LDREX/STREX, are routed through AXI master port 1, and transfers for even-numbered cores are routed through AXI master port 0.

The SCU also contains:

You can configure the event monitor for each core to gather statistics on the operation of the SCU.

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