2.5.8 Private memory region

All registers accessible by all cores within a Cortex®‑R8 processor design are grouped into two contiguous 4KB pages accessed through a dedicated internal bus.

The base address of these pages is defined by the configuration signal PERIPHBASE[31:13] inputs.

Global control registers and peripherals must be accessed through memory-mapped transfers to the private memory region.

Memory regions used for these registers must be marked as Device or Strongly-Ordered in the MPU.

Access to the private memory region is little-endian only.

Access these registers with single load/store instructions. Load or store multiple accesses cause an abort to the requesting core and the Fault Status Register shows this as a SLVERR.

The following table shows the permitted access sizes for the private memory regions.

Table 2-12 Permitted access sizes for private memory regions

Private memory region Permitted access sizes
Byte Halfworda Wordb Doubleworda
Global timer, private timers, and watchdogs No No Yes No
SCU registers Yes No Yes No
Processor interrupt interfaces
Interrupt distributor

The ACP cannot access any of the registers in this memory region.

The following table shows register addresses for the Cortex‑R8 processor relative to this base address.

Table 2-13 Cortex‑R8 processor private memory region

Offset from PERIPHBASE[31:13] Peripheral Description
0x0000-0x00FF SCU registers 9.3 SCU registers
0x0100-0x01FF Interrupt controller interfaces 9.4 Interrupt controller
0x0200-0x02FF Global timer 9.6 Global timer
0x0300-0x03FF Reserved Any access to this region causes an SLVERR abort exception
0x0400-0x04FF
0x0500-0x05FF
0x0600-0x06FF Private timers and watchdogs 9.5 Private timer and watchdog
0x0700-0x07FF Reserved Any access to this region causes an SLVERR abort exception
0x0800-0x08FF
0x0900-0x09FF
0x0A00-0x0AFF
0x0B00-0x0FFF
0x1000-0x1FFF Interrupt Distributor 9.4.4 Distributor register descriptions
a Halfword or doubleword accesses cause an abort to the requesting core and the Fault Status Register shows this as a SLVERR.
b A word access with strobes not all set causes an abort to the requesting core and the Fault Status Register shows this as a SLVERR.
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