12.3 Accessing RAMs using the AXI3 interface

The Cortex®‑R8 processor has a single AXI TCM slave port. The port is 64 bits wide and conforms to the AXI standard. Within the AXI standard, the slave port uses the AWUSERST and ARUSERST each as two separate chip select input signals to enable access to the TCMs as shown in the following table.

Table 12-11 TCM accesses

AxUSERST[2:0] value TCM
0b000 Instruction TCM of core 0
0b001 Data TCM of core 0
0b010 Instruction TCM of core 1
0b011 Data TCM of core 1
0b100 Instruction TCM of core 2
0b101 Data TCM of core 2
0b110 Instruction TCM of core 3
0b111 Data TCM of core 3

The external AXI system must generate the chip select signals. The AXI TCM slave interface routes the access to the required RAM.

The following table shows the MSB bit for the different TCM RAM sizes.

Table 12-12 MSB bit for the different TCM RAM sizes

TCM size ARADDRST[MSB]
4KB [11]
8KB [12]
16KB [13]
32KB [14]
64KB [15]
128KB [16]
256KB [17]
512KB [18]
1024KB [19]

ARADDRST[19:3] indicates the address of the doubleword in the TCM that you want to access. If you are accessing a TCM that is smaller than the maximum 1024KB, then it is possible to address a doubleword that is outside of the physical size of the TCM.

An access to the TCM RAMs is given an SLVERR error response if:

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