4.2.6 c9 registers

Summary of the 32-bit wide CP15 system control registers when CRn is c9.

Table 4-7 c9 register summary

Op1 CRm Op2 Name Reset Description
0 c1 0 DTCMRR UNK 4.3.13 DTCM Region Register
1 ITCMRR UNK 4.3.14 ITCM Region Register
c12 0 PMCR 0x41184000 Performance Monitor Control Registera
1 PMCNTENSET 0x00000000 Count Enable Set Registera
2 PMCNTENCLR 0x00000000 Count Enable Clear Registera
3 PMOVSR 0x00000000 Overflow Flag Status Registera
4 PMSWINC UNK Software Increment Registera
5 PMSELR 0x00000000 Event Counter Selection Registera
c13 0 PMCCNTR UNK Cycle Count Registera
1 PMXEVTYPER UNK Event Selection Registera
2 PMXEVCNTR UNK Performance Monitor Count Registersa
c14 0 PMUSERENR 0x00000000 User Enable Registera
1 PMINTENSET 0x00000000 Interrupt Enable Set Registera
2 PMINTENCLR 0x00000000 Interrupt Enable Clear Registera
a For information, see the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.
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