2.5.3 AXI low-latency peripheral port

The AXI low-latency peripheral port is a dedicated memory-mapped 32-bit AXI bus. It is used to access certain peripherals with a low latency and having burst support. The memory mapping is done by address filtering.

The following table shows the AXI low-latency port attributes.

Table 2-3 AXI low-latency port attributes

Attribute Format
Write issuing capability

15

Read issuing capability

15

Combined issuing capability 30
Write interleave capability 1.

The AXI peripheral port has optional ECC protection on data and parity on control bits.

This port does not support locked writes. AWLOCKMP[1] is always 0b0.

The AXI peripheral port does not support 64-bit accesses, including instruction fetches. These accesses always abort. Processor cacheable accesses mapped to the peripheral port also abort, because they are doing linefill requests, that is, four 64-bit accesses. Normal memory accesses to the peripheral port also abort. These accesses abort because of their size, not because of their memory attributes.

Any access in the address range between the peripheral filtering start address and the peripheral filtering end address is issued on the AXI peripheral port. All other accesses outside of this range are directed onto the AXI master ports. The start and end addresses are configurable in the following SCU registers:

The granularity of the mapped memory is 1MB and is defined by the formula:

Memory_space (MB) = End to Start + 1.

This filtering rule is applied independently of the AXI request type and attributes. .

This port supports five bits of AXI IDs, although AXI IDs can be larger if the ACP has more than four bits of ID. For example, if the ACP ID has four bits, there are five bits on the AXI peripheral port. If the ACP ID has eight bits, there are nine bits on the AXI peripheral port.

Note:

  • ID bit encoding is used to differentiate between different types of traffic happening in parallel. The encoding of the IDs is implementation specific.
  • If the address filtering of the peripheral port, and the address filtering of AXI master port 1 overlap, the peripheral port has priority.
  • If the address filtering of the fast peripheral port, and the address filtering of the peripheral port overlap, the fast peripheral port has priority.
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