7.4.2 ECC on external
All master buses, that is, AXI master port 0 and AXI master port 1, AXI low-latency peripheral port, AXI fast peripheral port, and the optional AXI TCM slave port, generate ECC check bits that are computed on all signals of the bus for write accesses, such as payload and control, including the AXI valid and AXI ready signals.
For read accesses, the complete bus is decoded:
- For single-bit errors, an inline correction
is provided. A primary error detection notification output signal
is raised at the same time. The inline correction implies some extra
cycles of memory latency.
- Double-bit errors only raise a primary error detection
notification output signal. The system must determine the correct
action in this case, such as an interrupt to the processor.
An external write access must be decoded on the ACP:
- A single-bit error is corrected inline
and a primary error detection notification output signal is raised.
- A double-bit error raises only a primary error detection
notification output signal.
An external read access encodes all signals of the bus, such
as payload and control, including the AXI valid and AXI ready signals.
- ECC is only present on data
buses. All other signals are protected by parity.
- ECC on the ACP bus is supported only when the ACP
bridge is implemented.
- For build options with ACP or TCM, when byte line
strobes are sparse on an ACP or a TCM slave port write access, the
unused bytes are masked in the processor and assumed to be driven
LOW. This is because the ECC is computed on a 64-bit chunk. Therefore,
a master driving the ACP or the TCM slave port must compute the
ECC bits together with the write data with the same assumption.
If ECC errors are found on TCM RAMs:
- For reads, the slave error is reported
for a fatal error. If the error is fatal, the FATALRAMERR output
is also raised. If the error is correctable, it is corrected internally
and no error is reported.
- For writes, no response is sent. If a fatal error
occurs, the FATALRAMERR output is raised.
You can configure whether this logic is present in the
To enable ECC in the
processor, you must first enable
ECC on the RAMs.