7.4.2 ECC on external AXI bus

All master buses, that is, AXI master port 0 and AXI master port 1, AXI low-latency peripheral port, AXI fast peripheral port, and the optional AXI TCM slave port, generate ECC check bits that are computed on all signals of the bus for write accesses, such as payload and control, including the AXI valid and AXI ready signals.

For read accesses, the complete bus is decoded:

An external write access must be decoded on the ACP:

An external read access encodes all signals of the bus, such as payload and control, including the AXI valid and AXI ready signals.

Note:

  • ECC is only present on data buses. All other signals are protected by parity.
  • ECC on the ACP bus is supported only when the ACP bridge is implemented.
  • For build options with ACP or TCM, when byte line strobes are sparse on an ACP or a TCM slave port write access, the unused bytes are masked in the processor and assumed to be driven LOW. This is because the ECC is computed on a 64-bit chunk. Therefore, a master driving the ACP or the TCM slave port must compute the ECC bits together with the write data with the same assumption.

If ECC errors are found on TCM RAMs:

You can configure whether this logic is present in the Cortex®‑R8 processor.

Note:

To enable ECC in the Cortex‑R8 processor, you must first enable ECC on the RAMs.
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.