11.8.15 ViewInst Include/Exclude Control Register

The TRCVIIECTLR defines the address range comparators that control the ViewInst Include/Exclude control.

Usage constraints
Can only be written when the Cortex®‑R8 processor ETM is disabled.
Configurations
Available in all configurations.
Attributes

Register number: 33

Base offset 0x084

Name: TRCVIIECTLR

Type: RW

Reset: -

The following figure shows the TRCVIIECTLR bit assignments.

Figure 11-19 TRCVIIECTLR bit assignments
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The following table shows the TRCVIIECTLR bit assignments.

Table 11-31 TRCVIIECTLR bit assignments

Bits Name Function
[31:20] - Reserved. RAZ/WI.
[19:16] EXCLUDE Defines the address range comparators for ViewInst exclude control. One bit is provided for each implemented Address Range Comparator.
[15:4] - Reserved. RAZ/WI.
[3:0] INCLUDE

Defines the address range comparators for ViewInst include control.

Selecting no include comparators indicates that all instructions must be included. The exclude control indicates which ranges must be excluded.

One bit is provided for each implemented Address Range Comparator.

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