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The Cortex®‑R8 processor master ports can generate all possible AXI3 transactions from ACP traffic, including transaction types that differ from that of the original ACP transaction.
Transactions from the individual cores use only the following subset of possible AXI3 transactions:
For cacheable transactions:
WRAP4 64-bit for read transfers (linefills).
For Non-Cacheable transactions:
WRAP4 64-bit for NC reads from instruction cache.
The following points apply to AXI3 transactions: