11.8.38 Single-Shot Comparator Status Registers 0-1

The TRCSSCSRn indicate the status of the single-shot comparators. TRCSSCSR0 is sensitive to instruction addresses. TRCSSCSR1 is sensitive to data addresses and values.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Register number: 168-169

Base offset 0x2A0-0x2A4

Name: TRCSSCSRn

Type: RW

Reset: -

The following figure shows the TRCSSCSRn bit assignments.

Figure 11-47 TRCSSCSRn bit assignments
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The following table shows the TRCSSCSR0 bit assignments.

Table 11-59 TRCSSCSR0 bit assignments

Bits Name Function
[31] STATUS

Single-shot status. This indicates whether any of the selected comparators have matched:

0b0Match has not occurred.
0b1Match has occurred at least once.

When programming the Cortex®‑R8 processor ETM, if TRCSSCCRn.RST is 0b0, the STATUS bit must be explicitly written to 0b0 to enable this single-shot comparator control.

[30:3] - Reserved. RAZ/WI.
[2] DV

Data value comparator support:

0b0Single-shot data value comparisons not supported.
[1] DA

Data address comparator support:

0b0Single-shot data address comparisons not supported.
[0] INST

Instruction address comparator support:

0b1Single-shot instruction address comparisons supported.

The following table shows the TRCSSCSR1 bit assignments.

Table 11-60 TRCSSCSR1 bit assignments

Bits Name Function
[31] STATUS

Single-shot status. This indicates whether any of the selected comparators have matched:

0b0Match has not occurred.
0b1Match has occurred at least once.

When programming the Cortex‑R8 processor ETM, this bit must be explicitly written to 0b0 to enable this single-shot comparator control.

[30:3] - Reserved. RAZ/WI.
[2] DV

Data value comparator support:

0b1Single-shot data value comparisons supported.
[1] DA

Data address comparator support:

0b1Single-shot data address comparisons supported.
[0] INST

Instruction address comparator support:

0b0Single-shot instruction address comparisons not supported.
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