11.1.2 Features

The Cortex®‑R8 processor ETM supports tracing of 32-bit ARM® instructions, and 16-bit and 32-bit Thumb® instructions.

See the ARM® Embedded Trace Macrocell Architecture Specification ETMv4 for information about:

  • The trace protocol.
  • The features of ETMv4.
  • Controlling tracing using triggering and filtering resources.
  • ETM sharing.

The following table shows the features of the Cortex‑R8 processor ETM that are implementation-defined, in terms of either:

  • The number of times the feature is implemented.
  • The size of the feature.

Table 11-1 Cortex‑R8 processor ETM features with implementation-defined number of instances or size

Feature Cortex‑R8 processor ETM value Notes
Address comparators 4 pairs See bits[3:0] of the 11.8.34 ID Register 4
Data value comparators 2 See bits[7:4] of the 11.8.34 ID Register 4  
Context ID comparators 1 See bits[27:24] of the 11.8.34 ID Register 4
Single-Shot comparator resource 2, one for instruction, one for data See bits[2:0] of the 11.8.38 Single-Shot Comparator Status Registers 0-1
Counters 2 See bits[30:28] of the 11.8.35 ID Register 5
Cycle count size 12 See bits[28:25] of the 11.8.32 ID Register 2
Sequencer 1 One four-state sequencer. See bits[27:25] of the 11.8.35 ID Register 5. 
Core comparator inputs Not implemented See bits[15:12] of the 11.8.34 ID Register 4
External inputs 64 See bits[8:0] of the 11.8.35 ID Register 5
External outputs 4 See bits[3:0] of the 11.8.7 Event Control 1 Register
External input selectors 4 See bits[11:9] of the 11.8.35 ID Register 5
Resource selector pairs 8 See bits[19:16] of the 11.8.34 ID Register 4
Instruction trace port size 32-bit -
Data trace port size 64-bit -
Instruction FIFOa 128 byte with 32-bit output Uses ATB
Data FIFO 256 byte with 64-bit output Uses ATB
Claim tag bits 4 See bits[3:0] of the 11.8.50 Claim Tag Set Register

The following table shows the optional features of the ETM architecture that the Cortex‑R8 processor ETM implements.

Table 11-2 Cortex‑R8 processor ETM implementation of optional features

Feature Implemented? Notes
Configurable FIFO No -
Trace Start/Stop block Yes 11.8.16 ViewInst Start/Stop Control Register
Trace all branches option Yes See bit[5] of the 11.8.30 ID Register 0
Trace of conditional instructions Yes See bits[13:12] and bit[6] of the 11.8.30 ID Register 0, using the full CPSR value
Cycle counting in instruction trace Yes See bit[7] of the 11.8.30 ID Register 0
Data trace supported  Yes See bits[4:3] of the 11.8.30 ID Register 0
Data address comparison Yes See bit[8] of the 11.8.34 ID Register 4
OS Lock mechanism Yes 11.8.39 OS Lock Access Register
Secure non-invasive debug No The Cortex‑R8 processor does not implement the Security Extensions
Context ID tracing Yes See bits[9:5] of the 11.8.32 ID Register 2
Trace output Yes ATB
Timestamp size (48/64) System configurable See bits[28:24] of the 11.8.30 ID Register 0
Memory mapped access to ETM registers Yes -
System instruction access to ETM registers No -
VMID comparator support No See bits[31:28] of the 11.8.34 ID Register 4
ATB trigger support Yes See bit[22] of the 11.8.35 ID Register 5

a Instruction trace can be configured to take priority over data trace. See bit[10] of the TRCSTALLCTLR.
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.