12.2 Optimized accesses to the L2 memory interface

Optimized accesses to the L2 memory interface can generate non-AXI3 compliant requests on the AXI master ports. These non-AXI compliant requests must be generated only when the slaves connected on the AXI master ports can support them. The L2C-310 Cache Controller supports these types of requests.

This section contains the following subsections:
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.