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To enable data cache coherency in the cores, set the SMP bit, bit in the Auxiliary Control Register (the reset value is zero), and set the SCU enable bit, bit in the SCU Control Register (the reset value is zero).
The L1 data cache coherency between the cores is done in the inner Write-Back, Write-Allocate Shareable memory regions. The coherency between the ACP traffic and the L1 data cache of the cores is triggered when AxUSERSC = 1 and AxCACHESC = 1.