10.1.1 PMU register mappings

The PMU counters, and their associated control registers, are accessible from the internal CP15 interface and from the Debug APB interface.

The following table shows the mappings of the PMU registers.

Table 10-1 Performance monitoring instructions and Debug APB mapping

Debug APB interface mapping CP15 instruction Access Reset Name
0x000 0, c9, c13, 2 RW - PMXEVCNTR0
0x004 0, c9, c13, 2 RW - PMXEVCNTR1
0x008 0, c9, c13, 2 RW - PMXEVCNTR2
0x00C 0, c9, c13, 2 RW - PMXEVCNTR3
0x010 0, c9, c13, 2 RW - PMXEVCNTR4
0x014 0, c9, c13, 2 RW - PMXEVCNTR5
0x018 0, c9, c13, 2 RW - PMXEVCNTR6
0x01C 0, c9, c13, 2 RW - PMXEVCNTR7
0x07C 0, c9, c13, 0 RW - PMCCNTR
0x400 0, c9, c13, 1 RW - PMXEVTYPER0
0x404 0, c9, c13, 1 RW - PMXEVTYPER1
0x408 0, c9, c13, 1 RW - PMXEVTYPER2
0x40C 0, c9, c13, 1 RW - PMXEVTYPER3
0x410 0, c9, c13, 1 RW - PMXEVTYPER4
0x414 0, c9, c13, 1 RW - PMXEVTYPER5
0x418 0, c9, c13, 1 RW - PMXEVTYPER6
0x41C 0, c9, c13, 1 RW - PMXEVTYPER7
0xC00 0, c9, c12, 1 RW - PMCNTENSET
0xC20 0, c9, c12, 2 RW - PMCNTENCLR
0xC40 0, c9, c14, 1 RW - PMINTENSET
0xC60 0, c9, c14, 2 RW - PMINTENCLR
0xC80 0, c9, c12, 3 RW - PMOVSR
0xCA0 0, c9, c12, 4 WO - PMSWINC
0xE04 0, c9, c12, 0 RW 0x41184000 PMCR
0xE08 0, c9, c14, 0 RWa 0x00000000 PMUSERENR
- 0, c9, c12, 5 RW - PMSELR
a Read only in user mode.
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