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The Cortex®‑R8 processor L2 interface consists of one or two 64-bit wide AXI3 bus masters. AXI3 M0 is always present. AXI3 M1 is optional and supports address filtering.
The following table shows the AXI3 master 0 and master 1 interface attributes.
Table 12-1 AXI3 master 0 and master 1 interface attributes
|Write issuing capability||
29 + 12 * CNa for an implementation with CN + 1 cores, including:
|Read issuing capability||
31 + 16 * CNa for an implementation with CN + 1 cores, including:
|Combined issuing capability||60 + 28 * CNa.|
|Write interleave capability||1.|
The AXI3 protocol and meaning of each AXI3 signal are not described in this document. For more information see the ARM AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite.