12.1 About the L2 interface

The Cortex®‑R8 processor L2 interface consists of one or two 64-bit wide AXI3 bus masters. AXI3 M0 is always present. AXI3 M1 is optional and supports address filtering.

The following table shows the AXI3 master 0 and master 1 interface attributes.

Table 12-1 AXI3 master 0 and master 1 interface attributes

Attribute Format
Write issuing capability

29 + 12 * CNa for an implementation with CN + 1 cores, including:

  • 15 ACP writes.
  • For each core:

    • Eight Non-Cacheable writes.

    • Four evictions.
  • Two coherency operation evictions.
Read issuing capability

31 + 16 * CNa for an implementation with CN + 1 cores, including:

  • 15 ACP reads.
  • For each core:

    • Four data side linefill reads.

    • Eight instruction side linefill reads.
    • Four Non-Cacheable reads.
Combined issuing capability 60 + 28 * CNa.
Write interleave capability 1.

Note:

The numbers given in the table are the theoretical maximums for the Cortex‑R8 processor. A typical system is unlikely to reach these numbers. ARM recommends that you perform profiling to tailor your system resources appropriately for optimum performance.

The AXI3 protocol and meaning of each AXI3 signal are not described in this document. For more information see the ARM AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite.

This section contains the following subsections:
a CN represents the number of configured cores minus one.
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.