9.3.4 SCU Invalidate All Register

The SCU Invalidate All Register invalidates the SCU tag RAMs on a per core, and per way basis.

Usage constraints
  • This register invalidates all lines in the selected ways.
  • Writes to this register are enabled when the access bit for the core is set in the SCU Access Control Register. See 9.3.9 SCU Access Control Register.
Configurations
Available in all configurations.
Attributes

Offset from PERIPHBASE[31:13]: 0x0C

Reset value: 0x0

The following figure shows the SCU Invalidate All Register bit assignments.

Figure 9-5 SCU Invalidate All Register bit assignments
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The following table shows the SCU Invalidate All Register bit assignments.

Table 9-6 SCU Invalidate All Register bit assignments

Bits Name Description
[31:16]   Reserved. SBZ.
[15:12] Core 3 ways Specifies the ways that must be invalidated for core 3. Writing to these bits has no effect if the Cortex®‑R8 processor has fewer than four cores.
[11:8] Core 2 ways Specifies the ways that must be invalidated for core 2. Writing to these bits has no effect if the Cortex‑R8 processor has fewer than three cores.
[7:4] Core 1 ways Specifies the ways that must be invalidated for core 1. Writing to these bits has no effect if the Cortex‑R8 processor has fewer than two cores.
[3:0] Core 0 ways Specifies the ways that must be invalidated for core 0.
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