10.4 Debug

The Cortex®‑R8 processor implements the ARMv7 debug architecture and the set of debug events.

Refer to the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition for the debug architecture and debug events.


When the low-latency interrupt mode is enabled, ARM recommends that you set DBGDSCR.INTdis register bit, to disable interrupts before allowing the processor to enter debug state.
This section contains the following subsections:
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