6.6 Memory types and L1 memory system behavior

The behavior of the L1 memory system depends on the type attribute of the memory that is being accessed.

The following table summarizes the processor memory types and associated behavior.

Table 6-11 Memory types and associated behavior

Memory type Cacheable Merging Restartable Local exclusives Locked swaps
Normal Shareable -a Yes Yes Partiallyb Yes
Non-Shareable Yes Yes Yes Yes No
Device Shareable No No No Noc Noc
Non-Shareable No No No Noc Yes
Strongly Ordered Shareable No No No Noc Yes
a Depends on the value of the ACTLR.SMP bit: 1 = Cacheable. 0 = Non-Cacheable.
b Depends on the value of the ACTLR.SMP bit: 1 = Exclusive accesses handled using only local monitor. 0 = Exclusive accesses handled using both local and global monitor.
c Exclusive accesses are handled using both local and global monitor.
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