9.3 SCU registers

All SCU registers are memory-mapped and have a common base address. Addresses are relative to the base address of the region for the SCU memory map, PERIPHBASE[31:13].

To access the SCU registers, PERIPHBASE[31:13] must be located in the address range that PFILTERSTART[11:0] and PFILTEREND[11:0] define. The value of PERIPHBASE[31:13] can be retrieved by a core using the Configuration Base Address Register (CBAR) so that software can determine the location of the SCU registers.

The Peripheral End Address filtering must be greater than or equal to the Peripheral Start Address. The memory space in MB used for the address filtering is defined as follows:

The following table shows the peripheral accesses relative to the Peripheral Address setting.

Table 9-1 Peripheral accesses

Access SCU registers AXI low-latency peripheral port traffic
Accessible by any core Accessible through the ACP Accessible by any core or through the ACP
Peripheral End Address less than Peripheral Start Address No No Not enabled
Peripheral End Address equal to Peripheral Start Address Yes No Enabled
Peripheral End Address greater than Peripheral Start Address Yes No Enabled

The following table shows the SCU registers. All SCU registers are byte accessible and are reset by nSCURESET.

Table 9-2 SCU registers summary

Offset from PERIPHBASE[31:13] Name Reset value Page
0x00 SCU Control Register Implementation defined 9.3.1 SCU Control Register
0x04 SCU Configuration Register Implementation defined 9.3.2 SCU Configuration Register
0x08 SCU CPU Power Status Register - 9.3.3 SCU CPU Power Status Register
0x0C SCU Invalidate All Registers 0x0 9.3.4 SCU Invalidate All Register
0x40 Master Filtering Start Address Register Defined by MFILTERSTART input 9.3.5 Master Filtering Start Address Register
0x44 Master Filtering End Address Register Defined by MFILTEREND input 9.3.6 Master Filtering End Address Register
0x48 Peripherals Filtering Start Address Register Defined by PFILTERSTART input 9.3.7 LLP Filtering Start Address Register
0x4C Peripherals Filtering End Address Register Defined by PFILTEREND input 9.3.8 LLP Filtering End Address Register
0x50 SCU Access Control Register 0b11 9.3.9 SCU Access Control Register
0x60 SCU Error Bank First Entry Registera - 9.3.10 SCU Error Bank First Entry Register
0x64 SCU Error Bank Second Entry Registera - 9.3.11 SCU Error Bank Second Entry Register
0x70 SCU Debug Tag RAM Operation Register - SCU Debug Tag RAM Operation Register
0x74 SCU Debug Tag RAM Data Value Register - SCU Debug Tag RAM Data Value Register
0x78 SCU Debug Tag RAM ECC Chunk Registera - SCU Debug Tag RAM ECC Chunk Register
0x7C ECC Fatal Error Registera 0x0 9.3.14 FPP Filtering Start Address Registers 0-3
0x80 FPP Filtering Start Address Register for core 0 Defined by FPFILTERSTART0 9.3.14 FPP Filtering Start Address Registers 0-3
0x84 FPP Filtering End Address Register for core 0 Defined by FPFILTEREND0 9.3.15 FPP Filtering End Address Registers 0-3
0x88 FPP Filtering Start Address Register for core 1 Defined by FPFILTERSTART1 9.3.14 FPP Filtering Start Address Registers 0-3
0x8C FPP Filtering End Address Register for core 1 Defined by FPFILTEREND1 9.3.15 FPP Filtering End Address Registers 0-3
0x90 FPP Filtering Start Address Register for core 2 Defined by FPFILTERSTART2 9.3.14 FPP Filtering Start Address Registers 0-3
0x94 FPP Filtering End Address Register for core 2 Defined by FPFILTEREND2 9.3.15 FPP Filtering End Address Registers 0-3
0x98 FPP Filtering Start Address Register for core 3 Defined by FPFILTERSTART3 9.3.14 FPP Filtering Start Address Registers 0-3
0x9C FPP Filtering End Address Register for core 3 Defined by FPFILTEREND3 9.3.15 FPP Filtering End Address Registers 0-3
This section contains the following subsections:
a This register is present only when ECC is implemented.
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