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Details of the debug signals.
Table A-48 Debug signals
|EDBGRQ[CN:0]||Input||External debug device||
Individual core external debug request:
The core treats the EDBGRQ input as level sensitive. The EDBGRQ input must be asserted until the core asserts DBGACK.
|DBGACK[CN:0]||Output||Individual core debug acknowledge signal. Acknowledges that the corresponding core has entered debug state after an external debug request.|
|DBGCPUDONE[CN:0]||Output||Acknowledges that corresponding core has entered debug state and that all previous non-debug state memory accesses are complete.|
|DBGNOPWRDWN[CN:0]||Output||Output reflecting the value of DBGPRCR. See the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.|
When LOW only the external debug agent can modify debug registers:
|DBGROMADDR[31:12]||Input||External debug device||
CoreSight™ System configuration. Specifies bits[31:12] of the ROM table physical address.
If the address cannot be determined, tie off this signal to zero.
Valid signal for DBGROMADDR.
If the address cannot be determined, tie this signal LOW.
Specifies bits[31:17] of the two’s complement signed offset from the ROM table physical address to the physical address where the debug registers are memory-mapped.
If the offset cannot be determined, tie off this signal to zero.
Valid signal for DBGSELFADDR.
If the offset cannot be determined, tie this signal LOW.