A.14.2 Debug signals

Details of the debug signals.

Table A-48 Debug signals

Name Type Source/destination Description
EDBGRQ[CN:0] Input External debug device

Individual core external debug request:

0b0No external debug request.
0b1External debug request.

The core treats the EDBGRQ input as level sensitive. The EDBGRQ input must be asserted until the core asserts DBGACK.

DBGACK[CN:0] Output Individual core debug acknowledge signal. Acknowledges that the corresponding core has entered debug state after an external debug request.
DBGCPUDONE[CN:0] Output Acknowledges that corresponding core has entered debug state and that all previous non-debug state memory accesses are complete.
DBGNOPWRDWN[CN:0] Output Output reflecting the value of DBGPRCR[0]. See the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.
DBGSWENABLE[CN:0] Input

When LOW only the external debug agent can modify debug registers:

0b0Not enabled.
0b1Enabled. Access by the software through the extended CP14 interface is permitted. External CP14 and external debug accesses are permitted.
DBGROMADDR[31:12] Input External debug device

CoreSight™ System configuration. Specifies bits[31:12] of the ROM table physical address.

If the address cannot be determined, tie off this signal to zero.

DBGROMADDRV Input

Valid signal for DBGROMADDR.

If the address cannot be determined, tie this signal LOW.

DBGSELFADDR[31:17] Input

Specifies bits[31:17] of the two’s complement signed offset from the ROM table physical address to the physical address where the debug registers are memory-mapped.

If the offset cannot be determined, tie off this signal to zero.

DBGSELFADDRV Input

Valid signal for DBGSELFADDR.

If the offset cannot be determined, tie this signal LOW.

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