11.8.21 Sequencer Reset Control Register

The TRCSEQRSTEVR resets the sequencer to state 0.

Usage constraints
Can only be written when the Cortex®‑R8 processor ETM is disabled.
Available in all configurations.

Register number: 70

Base offset 0x118


Type: RW

Reset: -

The following figure shows the TRCSEQRSTEVR bit assignments.

Figure 11-25 TRCSEQRSTEVR bit assignments
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The following table shows the TRCSEQRSTEVR bit assignments.

Table 11-37 TRCSEQRSTEVR bit assignments

Bits Name Function
[31:8] - Reserved. RAZ/WI.

Selects the resource type to move back to state 0:

0b0Single selected resource.
0b1Boolean combined resource pair.
[6:4] - Reserved. RAZ/WI.

Selects the resource number, based on the value of RESETTYPE:

When RESETTYPE is 0b0, selects a single selected resource from 0-15 defined by bits[3:0].

When RESETTYPE is 0b1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

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