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A Cortex®‑R8 processor that has either only one or only two cores can be implemented with a second, redundant copy of most of the logic. This is known as a dual-redundant configuration. The redundant logic includes a second core that shares the input pins and the cache and TCM of the primary core, so only one set of cache and TCM is required.
The redundant logic includes the second core logic, but not the ETM logic if an ETM is present. The redundant logic operates in lock-step with the primary core, but does not directly affect the primary core behavior in any way. The primary core drives the output pins and the RAMs. The redundant logic also includes a copy of:
Comparison logic can be included at build time. This logic compares the outputs of the primary core, SCU, and AXI TCM slave with those of their redundant copy. These comparators are enabled through the COMPENABLE input signal. If a fault occurs in either the primary or redundant logic because of radiation or circuit failure, the comparison logic detects it and asserts the COMPFAULT output signal. Used with the RAM error detection schemes, this can help protect the system from faults. COMPENABLE can be asserted only after an initialization phase, see the ARM® Cortex®‑R8 MPCore Processor Configuration and Sign-off Guide. See the ARM® Cortex®‑R8 MPCore Processor Integration Manual for more information about COMPENABLE and COMPFAULT or contact your system integrator.
ARM provides example comparison logic, but you can change this during implementation. If you are implementing a dual-redundant configuration, contact ARM for more information.