A.16 Memory reconstruction port signals

Details of the Cortex®‑R8 processor MRP signals. The x at the end of the signal name represents either core 0, core 1, core 2 or core 3.

Table A-57 Memory reconstruction port signals

Name Type Source/destination Description
MRPREADYx Input Trace analysis engine Ready signal of any write access
MRPVALIDx Output Valid signal of any write access
MRPADDRx[31:0] Output Address of any write access
MRPDATAx[63:0] Output Data of any write access
MRPSTRBx[7:0] Output Strobe of any write access
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