9.3.8 LLP Filtering End Address Register

The LLP Filtering End Address Register provides the filtering end address for the AXI low-latency peripheral port.

Usage constraints
This register is read-only. It has an inclusive address as its end address. This means that the topmost megabyte of address space of memory can be included in the filtering address range. For the peripheral port region to operate, the filtering start address must be lower than the filtering end address.
Configurations
Available in all configurations.
Attributes

Offset from PERIPHBASE[31:13]: 0x4C

Reset value: Defined by PFILTEREND input.

The following figure shows the LLP Filtering End Address Register bit assignments.

Figure 9-9 LLP Filtering End Address Register bit assignments
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The following table shows the LLP Filtering End Address Register bit assignments.

Table 9-10 LLP Filtering End Address Register bit assignments

Bits Name Description
[31:20] Filtering end address

Filtering end address for the peripheral port.

The default value is the value of PFILTEREND sampled on exit from reset. The value on the input gives the upper address bits with 1MB granularity.

[19:0]   Reserved. SBZ.

See A.5 Configuration signals. See also 2.5.3 AXI low-latency peripheral port.

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