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The LLP Filtering End Address Register provides the filtering end address for the AXI low-latency peripheral port.
Offset from PERIPHBASE[31:13]:
Reset value: Defined by PFILTEREND input.
The following figure shows the LLP Filtering End Address Register bit assignments.
The following table shows the LLP Filtering End Address Register bit assignments.
Table 9-10 LLP Filtering End Address Register bit assignments
|[31:20]||Filtering end address||
Filtering end address for the peripheral port.
The default value is the value of PFILTEREND sampled on exit from reset. The value on the input gives the upper address bits with 1MB granularity.