11.8.23 External Input Select Register

The TRCEXTINSELR controls the selectors that choose an external input as a resource in the Cortex®‑R8 processor ETM.

Usage constraints
Can only be written when the Cortex‑R8 processor ETM is disabled.
Configurations
Available in all configurations.
Attributes

Register number: 72

Base offset 0x120

Name: TRCEXTINSELR

Type: RW

Reset: -

The following figure shows the TRCEXTINSELR bit assignments.

Figure 11-27 TRCEXTINSELR bit assignments
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The following table shows the TRCEXTINSELR bit assignments.

Table 11-39 TRCEXTINSELR bit assignments

Bits Name Function
[31:30] - Reserved. RAZ/WI
[29:24] SEL3 Selects an event from the external input bus for External Input Resource 3
[23:22] - Reserved. RAZ/WI
[21:16] SEL2 Selects an event from the external input bus for External Input Resource 2
[15:14] - Reserved. RAZ/WI
[13:8] SEL1 Selects an event from the external input bus for External Input Resource 1
[7:6] - Reserved. RAZ/WI
[5:0] SEL0 Selects an event from the external input bus for External Input Resource 0
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