9.7.3 Write accesses in coherent mode

Behavior of write accesses from the ACP in coherent mode.

  • If data is present in the L1 data cache of a core, and:

    • If the cache line is clean, the line is invalidated, and the write is done on the L2 memory.

    • If the cache line is dirty, the line is cleaned and invalidated, and the write is done on the L2 memory.
  • If data is not present in the L1 data cache of a core, the data is written to the L2 memory.
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