11.8.16 ViewInst Start/Stop Control Register

The TRCVISSCTLR defines the single address comparators that control the ViewInst Start/Stop logic.

Usage constraints
Can only be written when the Cortex®‑R8 processor ETM is disabled.
Configurations
Available in all configurations.
Attributes

Register number: 34

Base offset 0x088

Name: TRCVISSCTLR

Type: RW

Reset: -

The following figure shows the TRCVISSCTLR bit assignments.

Figure 11-20 TRCVISSCTLR bit assignments
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The following table shows the TRCVISSCTLR bit assignments.

Table 11-32 TRCVISSCTLR bit assignments

Bits Name Function
[31:24] - Reserved. RAZ/WI.
[23:16] STOP

Defines the single address comparators to stop trace with the ViewInst Start/Stop control.

One bit is provided for each implemented single address comparator.

[15:8] - Reserved. RAZ/WI.
[7:0] START

Defines the single address comparators to start trace with the ViewInst Start/Stop control.

One bit is provided for each implemented single address comparator.

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